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ST72P361K9T3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST72P361K9T3' PDF : 224 Pages View PDF
ST72361
POWER SAVING MODES (Cont’d)
Figure 31. AWUFH Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
(AWUCSR.AWUEN=1)
WDGHALT 1)
1
WATCHDOG
RESET
ENABLE
0
WATCHDOG
DISABLE
AWU RC OSC ON
MAIN OSC
OFF
PERIPHERALS 2) OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT 3)
AWU RC OSC OFF
Y
MAIN OSC
ON
PERIPHERALS OFF
CPU
I[1:0] BITS
ON
XX 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
AWU RC OSC
MAIN OSC
PERIPHERALS
CPU
I[1:0] BITS
OFF
ON
ON
ON
XX 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only an AWUFH interrupt and some specific in-
terrupts can exit the MCU from HALT mode (such
as external interrupt). Refer to Table 9, “Interrupt
Mapping,” on page 33 for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
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