ST7567 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'ST7567' PDF : 73 Pages View PDF
ST7565S
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Table 25
Signal Symbol
tAH8
A0
tAW8
tCYC8
tCCLW
WR
tCCHW
tCCLR
RD
tCCHR
tDS8
tDH8
D0 to D7
tACC8
tOH8
Condition
CL = 100 pF
CL = 100 pF
(VDD = 2.7 V , Ta = 25°C )
Rating
Min.
Max.
Units
0
—
0
—
400
—
220
—
180
—
220
—
ns
180
—
40
—
0
—
—
140
10
100
Item
Address hold time
Address setup time
System cycle time
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
READ Output disable time
Table 26
Signal Symbol
tAH8
A0
tAW8
tCYC8
tCCLW
WR
tCCHW
tCCLR
RD
tCCHR
tDS8
tDH8
D0 to D7
tACC8
tOH8
Condition
CL = 100 pF
CL = 100 pF
(VDD = 1.8V , Ta = 25°C )
Rating
Min.
Max.
Units
0
—
0
—
640
—
360
—
280
—
360
—
ns
280
80
—
30
—
—
240
10
200
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.
Ver 0.3c
64/73
2002/07/22
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