ST75951 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST75951' PDF : 21 Pages View PDF
FUNCTIONAL DESCRIPTION (continued)
Figure 2
XTALIN
(MCLK)
XTALOUT MCM SCLK
M/S
8
7
4
2
14
VDD
%M
%Q
%R
Sync
% OVER
D5 27
F0
D6 26
%2
Internal Sampling
Frequency
%2
F0 or F0/2
ST75951
3 FS
GPIO2 or OH
GPIO1 or CL
4 - Power Down Mode
Two PowerDown modes are available in ST75951
thanks to bit 4 in control register 3.
4.1 - PowerDown Mode 0
If bit 4 is set to ’0’ then when PWRDWN is set to ’0’
the entire chip is in powerdown mode 0.
Figure 3
REG3 BIT4 = 0
Normal
PWRDWN
Power Down 0
Normal
4.2 - PowerDown Mode 1 (100µW)
When bit 4 is set to ’1’ then when PWRDWN is set
to ’0’ the chip is in powerdown except the Ring detect
circuitry (wake-up on Ring = powerdown mode 1).
The general purpose interrupt is also working in
order to wake-up the system for dedicated cus-
tomer feature associated with a defined GPIO (pro-
grammed as input and non-masked).
4.2.1 - Ring Bit and GPIO Bit Masked
In this configuration the processor relies on the
Ring output pin to process the wake-up of the
system and does not need the SSI to be powered-
on. The SSI will be put back in operative mode
when PWRDWN is set to ’1’ (see Figure 4).
4.2.2 - Ring Bit or GPIO Bit Non-Masked
In this configuration the processor relies on the SSI
to process the wake-up of the system and needs
the SSI to be powered-on.
On an incoming Ring signal or an interrupt coming
thanks to the GPIO, ST75951 will generate an
interrupt on GPI output pin and power-up the SSI,
the processor will be able to read the control regis-
ter 2 and find out the origine of the interrupt.
After a reading of the register 2, if the processor
does not set high PWRDWN ST75951 puts back
the SSI off in order to save energy (see Figure 5).
7/21
Share Link: 
