ST7715 View Datasheet(PDF) - Sitronix Technology Co., Ltd.
Part Name
Description
MFG CO.
'ST7715' PDF : 167 Pages View PDF
ST7715
8.2 Serial interface characteristics (3-line serial)
CSX
SCL
VIH
VIL
TCSS
SDA
VIH
VIL
SDA
(DOUT)
TSDS
TSCYCW/TSCYCR
TSHW/TSHR
TSLW/TSLR
TSDH
TACC
TCSH
VIH
TSCC
VIL
TCHW
TOH
VIH
VIL
VIH
VIL
Fig. 8.2.1 3-line serial interface timing
Signal
CSX
SCL
SDA
(DIN)
(DOUT)
Symbol
Parameter
TCSS
Chip select setup time (write)
TCSH
Chip select hold time (write)
TCSS
Chip select setup time (read)
TSCC
Chip select hold time (read)
TCHW Chip select “H” pulse width
TSCYCW Serial clock cycle (Write)
TSHW SCL “H” pulse width (Write)
TSLW
SCL “L” pulse width (Write)
TSCYCR Serial clock cycle (Read)
TSHR
SCL “H” pulse width (Read)
TSLR
SCL “L” pulse width (Read)
TSDS
Data setup time
TSDH
Data hold time
TACC
Access time
TOH
Output disable time
Min
15
15
60
65
40
66
30
30
150
60
60
10
10
10
Max
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
For maximum CL=30pF
For minimum CL=8pF
Table 8.2.1 3-line Serial Interface Characteristics
Note 1: VDDI=1.65 to 3.3V, VDD=2.6 to 3.3V, AGND=DGND=0V, Ta=25 ℃
Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30%
and 70% of VDDI for Input signals.
V1.5
23
2009-12-04
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