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ST7FDALI View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST7FDALI' PDF : 141 Pages View PDF
ST7DALI
OPERATING CONDITIONS (Cont’d)
The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.
13.3.4.1 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 4.5 to 5.5V
Symbol
Parameter
Conditions
Min Typ Max Unit
fRC
Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C,VDD=5V
quency
RCCR = RCCR02 ),TA=25°C,VDD=5V
760
1000
kHz
Accuracy of Internal RC TA=25°C,VDD=4.5 to 5.5V
-1
+1
%
ACCRC oscillator with
RCCR=RCCR02)
TA=-40 to +85°C,VDD=5V
TA=0 to +85°C,VDD=4.5 to 5.5V
-5
+2
%
-21)
+21)
%
IDD(RC)
RC oscillator current con-
sumption
TA=25°C,VDD=5V
9701)
µA
tsu(RC)
fPLL
tLOCK
tSTAB
ACCPLL
tw(JIT)
JITPLL
IDD(PLL)
RC oscillator setup time
x8 PLL input clock
PLL Lock time5)
PLL Stabilization time5)
TA=25°C,VDD=5V
x8 PLL Accuracy
fRC = 1MHz@TA=25°C,VDD=4.5 to 5.5V
fRC = 1MHz@TA=-40 to +85°C,VDD=5V
PLL jitter period
fRC = 1MHz
PLL jitter (fCPU/fCPU)
PLL current consumption TA=25°C
102)
µs
11)
MHz
2
ms
4
ms
0.14)
%
0.14)
%
83)
kHz
13)
%
6001)
µA
Notes:
1. Data based on characterization results, not tested in production
2. RCCR0 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ TA =25°C, VDD=5V. See “INTERNAL RC OS-
CILLATOR ADJUSTMENT” on page 23
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy.
5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11 on page 24.
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