ST7FLITE29 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE29
STMicroelectronics
'ST7FLITE29' PDF : 133 Pages View PDF
ST7LITE2
OPTION BYTES (Cont’d)
OPTION BYTE 1
OPT7 = PLLx4x8 PLL Factor selection.
0: PLLx4
1: PLLx8
OPT6 = PLLOFF PLL disable.
0: PLL enabled
1: PLL disabled (by-passed)
OPT5 = PLL32OFF 32MHz PLL disable.
0: PLL32 enabled
1: PLL32 disabled (by-passed)
OPT4 = OSC RC Oscillator selection
0: RC oscillator on
1: RC oscillator off
Notes:
1. 1% RC oscillator available on ST7LITE25 and
ST7LITE29 devices only
2. If the RC oscillator is selected, then to improve
clock stability and frequency accuracy, it is recom-
mended to place a decoupling capacitor, typically
100nF, between the VDD and VSS pins as close as
possible to the ST7 device.
OPT3:2 = LVD[1:0] Low voltage detection selec-
tion
These option bits enable the LVD block with a se-
lected threshold as shown in Table 23.
Table 23. LVD Threshold Configuration
Configuration
LVD1 LVD0
LVD Off
11
Highest Voltage Threshold (∼4.1V)
10
Medium Voltage Threshold (∼3.5V)
01
Lowest Voltage Threshold (∼2.8V)
00
OPT1 = WDG SW Hardware or Software
Watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT0 = WDG HALT Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Table 24. List of valid option combinations
Operating conditions
VDD range
Clock Source
PLL
off
Internal RC 1%1)
x4
2.4V - 3.3V
x8
External clock or oscillator
off
(depending on OPT6:4 selec- x4
tion)
x8
off
Internal RC 1% 1)
x4
x8
3.3V - 5.5V
External clock or oscillator
off
(depending on OPT6:4 selec- x4
tion)
x8
Typ fCPU
0.7MHz @3V
2.8MHz @3V
-
0-4MHz
4MHz
-
1MHz @5V
-
8MHz @5V
0-8MHz
-
8 MHz
OSC
0
0
-
1
1
-
0
-
0
1
-
1
Option Bits
PLLOFF
1
0
-
1
0
-
1
-
0
1
-
0
PLLx4x8
1
0
-
1
0
-
1
-
1
1
-
1
Note 1: Configuration available on ST7LITE25 and ST7LITE29 devices only
Note: see Clock Management Block diagram in Figure 13
123/133
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