ST7FLITE29 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE29
STMicroelectronics
'ST7FLITE29' PDF : 133 Pages View PDF
ST7LITE2
LITE TIMER (Cont’d)
11.3.4 Low Power Modes
Mode
Description
No effect on Lite timer
SLOW
(this peripheral is driven directly
WAIT
by fOSC/32)
No effect on Lite timer
ACTIVE-HALT No effect on Lite timer
HALT
Lite timer stops counting
11.3.5 Interrupts
Interrupt
Event
Event
Flag
Enable
Control
Bit
Timebase 1
Event
Timebase 2
Event
IC Event
TB1F
TB2F
ICF
TB1IE
TB2IE
ICIE
Exit
from
Wait
Yes
Yes
Yes
Exit
from
Active
Halt
Yes
No
No
Exit
from
Halt
No
No
No
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0 TB2IE TB2F
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 0 = TB2F Timebase 2 Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
LITE TIMER AUTORELOAD
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
REGISTER
7
0
AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0
Bits 7:0 = AR[7:0] Counter 2 Reload Value.
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
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