ST7FLITE29 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE29
STMicroelectronics
'ST7FLITE29' PDF : 133 Pages View PDF
ST7LITE2
LITE TIMER (Cont’d)
LITE TIMER COUNTER 2 (LTCNTR)
Read only
Reset Value: 0000 0000 (00h)
7
Bit 5 = TB Timebase period selection.
This bit is set and cleared by software.
0: Timebase period = tOSC * 8000 (1ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2ms @ 8
0
MHz)
CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0
Bits 7:0 = CNT[7:0] Counter 2 Reload Value.
This register is read by software. The LTARR val-
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR1)
Read / Write
Reset Value: 0x00 0000 (x0h)
7
0
ICIE ICF TB TB1IE TB1F -
-
-
Bit 7 = ICIE Interrupt Enable.
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the LTICR register. Writing to this bit
does not change the bit value.
0: No input capture
1: An input capture has occurred
Note: After an MCU reset, software must initialise
the ICF bit by reading the LTICR register
Bit 4 = TB1IE Timebase Interrupt enable.
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
Bit 3 = TB1F Timebase Interrupt Flag.
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No counter overflow
1: A counter overflow has occurred
Bits 2:0 = Reserved
LITE TIMER INPUT CAPTURE
(LTICR)
Read only
Reset Value: 0000 0000 (00h)
REGISTER
7
0
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits 7:0 = ICR[7:0] Input Capture Value
These bits are read by software and cleared by
hardware after a reset. If the ICF bit in the LTCSR
is cleared, the value of the 8-bit up-counter will be
captured when a rising or falling edge occurs on
the LTIC pin.
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