ST7LUS5, ST7LU05, ST7LU09
Supply, reset and clock management
6.2
6.2.1
Register description
Main clock control/status register (MCCSR)
MCCSR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
Reserved
MCO
SMS
-
R/W
R/W
Table 7. MCCSR register description
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) 6.2.2
Bit Name
Function
7:2 - Reserved, must be kept cleared.
Main clock out enable
1 MCO
This bit is read/write by software and cleared by hardware after a reset. This bit
allows to enable the MCO output clock.
0: MCO clock disabled; I/O port free for general purpose I/O
1: MCO clock enabled
Slow mode select
0 SMS
This bit is read/write by software and cleared by hardware after a reset. This bit
selects the input clock fOSC or fOSC/32.
0: Normal mode (fCPU = fOSCC)
1: Slow mode (fCPU = fOSCC/32)
RC control register (RCCR)
RCCR
Reset value: 1111 1111 (FFh)
7
6
5
4
3
2
1
0
CR[9:2]
R/W
Table 8. RCCR register description
Bit Name
Function
RC oscillator frequency adjustment bits
7:0 CR[9:2]
These bits, as well as CR[1:0] bits in the SICSR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. The application can store the correct value for each voltage
range in Flash memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a series of different values in the register until the
correct frequency is reached. The fastest method is to use a dichotomy starting with
80h.
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