ST7FLITEU0ICD View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FLITEU0ICD

8-bit low cost, low pin-count MCU for automotive, with single voltage Flash memory, ADC, timers

STMicroelectronics 

Prev 51 52 53 54 55 56 57 58 59 60 Next

ST7LUS5, ST7LU05, ST7LU09

Power saving modes

Figure 23. Halt mode flowchart

HALT instruction

(active halt disabled)

Enable

Watchdog

WDGHALT(1)

0

Disable

1

Watchdog

reset

Oscillator

Off

Peripherals(2) Off

CPU

Off

I bit

0

t(s) N

c Reset

du N

Y

ro ) Interrupt(3)

P t(s Y

Oscillator

On

te c Peripherals

Off

le u CPU

On

d I bit

X(4)

bso Pro 64 CPU clock cycle

- O te delay(5)

t(s) ole Oscillator

On

sPeripherals

On

c bCPU

On

u I bits

X(4)

rod ) - O Fetch reset vector

P t(s or service interrupt

lete uc 1. WDGHALT is an option bit. See option bytes in Section 14.1.1: Flash configuration for more details.

d 2. Peripheral clocked with an external clock source can still be active.

so ro 3. Only some specific interrupts can exit the MCU from halt mode (such as external interrupt). Refer to

b P Table 15: Interrupt mapping on page 46 for more details.

O te4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

Obsole5. The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering halt mode.

51/124

Share Link: