ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
Power saving modes
Figure 21. Active halt mode flowchart
Oscillator
On
HALT instruction
Peripherals(1)
Off
(active halt enabled) CPU
Off
I bit
0
N
Reset
N
Y
Interrupt(2)
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) 8.4.2
Y
Oscillator
On
Peripherals(1)
Off
CPU
On
I bit
X(3)
64 CPU clock cycle
delay
Oscillator
On
Peripherals
On
CPU
On
I bits
X(3)
Fetch reset vector
or service interrupt
1. Peripherals clocked with an external clock source can still be active.
2. Only the lite timer RTC and auto-reload timer interrupts can exit the MCU from active halt mode.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
Halt mode
The halt mode is the lowest power consumption mode of the MCU. It is entered by executing
the HALT instruction when active halt mode is disabled.
The MCU can exit halt mode on reception of either a specific interrupt (see Table 15:
Interrupt mapping on page 46) or a reset. When exiting halt mode by means of a reset or an
interrupt, the main oscillator is immediately turned on and the 64 CPU cycle delay is used to
stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or
by fetching the reset vector which woke it up (see Figure 30).
When entering halt mode, the I bit in the CC register is forced to 0 to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes immediately.
In halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
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