ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
On-chip peripherals
Input capture register high (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
15
0
0
0
0
ICR11
ICR10
ICR9
8
ICR8
Input capture register low (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
7
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
0
ICR0
● Bits 15:12 = Reserved.
● Bits 11:0 = ICR[11:0] Input capture data.
This is a 12-bit register which is readable by software and cleared by hardware after a
reset. The ATICR register contains captured the value of the 12-bit CNTR register when
a rising or falling edge occurs on the ATIC pin. Capture will only be performed when the
ICF flag is cleared.
Transfer control register (TRANCR)
Read/Write
Reset Value: 0000 0001 (01h)
7
0
0
0
0
0
0
0
0
TRAN
● Bits 7:1 Reserved. Forced by hardware to 0.
● Bit 0 = TRAN Transfer enable
This bit is read/write by software, cleared by hardware after each completed transfer
and set by hardware after reset.
It allows the value of the DCRx registers to be transferred to the DCRx shadow
registers after the next overflow event.
The OPx bits are transferred to the shadow OPx bits in the same way.
Doc ID 8349 Rev 5
83/166
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