ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
11.3.5
Interrupts
Table 38. TBxF and ICF interrupt events
Interrupt event
Event flag
Enable Control
bit
Exit from
WAIT
Timebase 1 event
TB1F
TB1IE
Yes
Timebase 2 event
TB2F
TB2IE
Yes
IC event
ICF
ICIE
Yes
Exit from
ACTIVE-
HALT
Yes
No
No
Exit from
HALT
No
No
No
Note:
11.3.6
The TBxF and ICF interrupt events are connected to separate interrupt vectors (see
Interrupts chapter).
They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the
interrupt mask in the CC register is reset (RIM instruction).
Register description
Lite timer control/status register 2 (LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
TB2IE
TB2F
● Bits 7:2 = Reserved, must be kept cleared.
● Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
● Bit 0 = TB2F Timebase 2 Interrupt Flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred.
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Doc ID 8349 Rev 5
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