ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7LITE20F2

8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI

STMicroelectronics 

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Data EEPROM

ST7LITE20F2 ST7LITE25F2 ST7LITE29F2

Table 4. Row definition

 Row / Byte 

0123

0

1

...

N

...

30 31

Physical address

00h...1Fh

20h...3Fh

Nx20h...Nx20h+1Fh

Figure 8. Data EEPROM Write operation

Read operation impossible

Read operation possible

E2LAT bit

E2PGM bit

Byte 1 Byte 2

Byte 32

Programming cycle

PHASE 1

Writing data latches

PHASE 2

Waiting E2PGM and E2LAT to fall

Set by USER application

Cleared by hardware

Note:

If a programming cycle is interrupted (by a reset action), the integrity of the data in memory

is not guaranteed.

5.4

Power saving modes

WAIT mode

The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the

microcontroller or when the microcontroller enters ACTIVE-HALT mode.The DATA EEPROM

will immediately enter this mode if there is no programming in progress, otherwise the DATA

EEPROM will finish the cycle and then enter WAIT mode.

ACTIVE-HALT mode

Refer to WAIT mode.

HALT mode

The DATA EEPROM immediately enters HALT mode if the microcontroller executes the

HALT instruction. Therefore the EEPROM will stop the function in progress, and data may

be corrupted.

5.5

Access error handling

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, then the data on the bus will not be latched.

If a programming cycle is interrupted (by a RESET action), the memory data will not be

guaranteed.

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Doc ID 8349 Rev 5

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