ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Data EEPROM
5.6
Note:
Data EEPROM Read-out protection
The Read-out protection is enabled through an option bit (see Section 15.1: Option bytes).
When this option is selected, the programs and data stored in the EEPROM memory are
protected against Read-out (including a re-write protection). In Flash devices, when this
protection is removed by reprogramming the Option Byte, the entire Program memory and
EEPROM is first automatically erased.
Both Program Memory and DATA EEPROM are protected using the same option bit.
Figure 9. Data EEPROM programming cycle
Internal
programming
voltage
Read operation not possible
Write of
data latches
Erase cycle
Write cycle
tPROG
Read operation possible
LAT
PGM
5.7
Note:
Register description
EEPROM Control/Status register (EECSR)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT E2PGM
● Bits 7:2 = Reserved, forced by hardware to 0.
● Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming
cycle. It can only be cleared by software if the E2PGM bit is cleared.
0: Read mode
1: Write mode
● Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
If the E2PGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
Doc ID 8349 Rev 5
27/166
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