ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
Power saving modes
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Note:
As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is
active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 26. ACTIVE-HALT timing overview
Run
Active-
halt
256 or 4096 CPU
cycle delay (1)
Run
HALT
instruction
[ACTIVE-HALT enabled]
Reset
or
interrupt
Fetch
vector
1. This delay occurs only if the MCU exits ACTIVE-HALT mode by means of a RESET.
Figure 27. ACTIVE-HALT mode Flow-chart
HALT instruction
(ACTIVE-HALT enabled)
(AWUCSR.AWUEN=0)
Oscillator
Peripherals (1)
CPU
I bit
ON
OFF
OFF
0
N
Reset
N
Y
Interrupt (2)
Y
Oscillator
ON
Peripherals (1) OFF
CPU
ON
I bit
X (3)
256 or 4096 CPU clock
cycle delay
Oscillator
ON
Peripherals
ON
CPU
ON
I bit
X (3)
Fetch reset vector
or service interrupt
1. Peripherals clocked with an external clock source can still be active.
2. Only the RTC1 interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode. Refer to
Table 12: Interrupt mapping for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
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Doc ID 8349 Rev 5
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