ST7LITE20F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE20F2
STMicroelectronics
'ST7LITE20F2' PDF : 166 Pages View PDF
Power saving modes
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Figure 29. AWUF halt timing diagram
tAWU
Run mode
HALT mode
fCPU
fAWU_RC
AWUF interrupt
256 or 4096 tCPU
Run mode
Clear
by software
Figure 30. AWUF mode flowchart
HALT instruction
(Active-halt disabled)
(AWUCSR.AWUEN=1)
WDGHALT (1)
1
Watchdog
reset
ENABLE
0
Watchdog
DISABLE
AWU RC osc
Main osc
Peripherals (2)
CPU
I[1:0] bits
ON
OFF
OFF
OFF
10
N
Reset
N
Y
Interrupt (3)
AWU RC osc OFF
Y
Main osc
ON
Peripherals
OFF
CPU
ON
I[1:0] bits
XX (4)
256 or 4096 CPU clock
cycle delay (5)
AWU RC osc
Main osc
Peripherals
CPU
I[1:0] bits
OFF
ON
ON
ON
XX (4)
Fetch RESET vector
or service interrupt
1. WDGHALT is an option bit (see Section 15.1: Option bytes for more details).
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUF interrupt and some specific interrupts can exit the MCU from HALT mode (such as external
60/166
Doc ID 8349 Rev 5
Share Link: 