ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
Interrupts
8
Interrupts
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Note:
Note:
8.1
8.2
The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt
(TRAP). The Interrupt processing flowchart is shown in Figure 20: Interrupt processing
flowchart.
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
Section : External interrupt function).
After reset, all interrupts are disabled.
When an interrupt has to be serviced:
● Normal processing is suspended at the end of the current instruction execution.
● The PC, X, A and CC registers are saved onto the stack.
● The I bit of the CC register is set to prevent additional interrupts.
● The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 12: Interrupt
mapping for vector addresses).
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority
defines which one will be serviced first (see Table 12: Interrupt mapping).
Interrupts and low power mode
All interrupts allow the processor to leave the WAIT low power mode. Only external and
specifically mentioned interrupts allow the processor to leave the HALT low power mode
(refer to the “Exit from HALT“ column in Table 12: Interrupt mapping).
Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It will be serviced according to the flowchart on Figure 20: Interrupt processing
flowchart.
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low power mode.
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Doc ID 8349 Rev 5
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