ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Interrupts
Note:
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in Section 10: I/O ports), a low
level on an I/O pin configured as input with interrupt, masks the interrupt request even in
case of rising edge sensitivity.
8.3
Note:
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
● The I bit of the CC register is cleared.
● The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
● writing “0” to the corresponding bit in the status register or
● access to the status register while the flag is set followed by a read or write of an
associated register.
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being
enabled) will therefore be lost if the clear sequence is executed.
Figure 20. Interrupt processing flowchart
FROM RESET
I BIT SET?
N
Y
FETCH NEXT INSTRUCTION
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Doc ID 8349 Rev 5
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