ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
10 I/O ports
I/O ports
10.1
Introduction
The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on chip peripherals or analog input.
10.2
10.2.1
Note:
Functional description
A Data Register (DR) and a Data Direction Register (DDR) are always associated with each
port.
The Option Register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer to
Section 10.7: Device-specific I/O port configuration for device specific information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit
x corresponding to pin x of the port.
Figure 31 shows the generic I/O block diagram.
Input modes
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: floating or pull-
up. Refer to I/O Port Implementation section for configuration.
Writing to the DR modifies the latch value but does not change the state of the input pin.
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an
interrupt request via the corresponding interrupt vector (eix).
Falling or rising edge sensitivity is programmed independently for each interrupt vector. The
External Interrupt Control Register (EICR) or the Miscellaneous Register controls this
sensitivity, depending on the device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description in Section 2: Pin description and Section : Interrupts.
If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they
are logically combined. For this reason if one of the interrupt pins is tied low, it may mask the
others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
Doc ID 8349 Rev 5
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