ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
On-chip peripherals
The LTICR is a read-only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
Timebase counter 2
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR
register. After an MCU reset, it increments at a frequency of fOSC/32 starting from the value
stored in the LTARR register. A counter overflow event occurs when the counter rolls over
from FFh to the LTARR reload value. Software can write a new value at anytime in the
LTARR register, this value will be automatically loaded in the counter when the next overflow
occurs.
When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an
interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software
reading the LTCSR2 register.
Figure 41. Input capture timing diagram
fCPU
4µs
(@ 8MHz fOSC)
fOSC/32
8-bit COUNTER 1 01h
02h
03h
04h
05h
06h
07h
CLEARED
BY S/W
READING
LTIC REGISTER
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
04h
07h
t
11.3.4
Low power modes
Table 37. Effect of low power modes on Lite timer
Mode
Description
SLOW
WAIT
ACTIVE-HALT
HALT
No effect on Lite timer
(this peripheral is driven directly by fOSC/32)
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
Doc ID 8349 Rev 5
87/166
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