ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
0: Timebase period = tOSC * 8000 (1 ms @ 8 MHz)
1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz)
● Bit 4 = TB1IE Timebase interrupt enable
This bit is set and cleared by software.
0: Timebase (TB1) interrupt disabled
1: Timebase (TB1) interrupt enabled
● Bit 3 = TB1F Timebase interrupt flag
This bit is set by hardware and cleared by software reading the LTCSR register. Writing
to this bit has no effect.
0: No counter overflow
1: A counter overflow has occurred
● Bit 2:0 = reserved.
Lite timer input capture register (LTICR)
Read only
Reset Value: 0000 0000 (00h)
7
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
0
ICR0
● Bits 7:0 = ICR[7:0] Input capture value
These bits are read by software and cleared by hardware after a reset. If the ICF bit in
the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or
falling edge occurs on the LTIC pin.
Table 39.
Address
(Hex.)
Lite timer register map and reset values
Register
Label
7
6
5
4
08
LTCSR2
Reset Value
0
0
0
0
09
LTARR
AR7
Reset Value 0
AR6
0
AR5
0
AR4
0
0A
LTCNTR
CNT7 CNT6 CNT5 CNT4
Reset Value 0
0
0
0
0B
LTCSR1
ICIE
Reset Value 0
ICF
x
TB TB1IE
0
0
0C
LTICR
ICR7
Reset Value 0
ICR6
0
ICR5
0
ICR4
0
3
0
AR3
0
CNT3
0
TB1F
0
ICR3
0
2
0
AR2
0
CNT2
0
0
ICR2
0
1
TB2IE
0
AR1
0
CNT1
0
0
ICR1
0
0
TB2F
0
AR0
0
CNT0
0
0
ICR0
0
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Doc ID 8349 Rev 5
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