ST7MDT1-DVP2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7MDT1-DVP2
STMicroelectronics
'ST7MDT1-DVP2' PDF : 140 Pages View PDF
ST72104G, ST72215G, ST72216G, ST72254G
I/O PORTS (Cont’d)
10.4 LOW POWER MODES
Mode
WAIT
HALT
Description
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
External interrupt on
selected external
-
event
DDRx
ORx
Yes
Exit
from
Halt
Yes
10.6 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B or C.
Read /Write
Reset Value: 0000 0000 (00h)
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7:0 = D[7:0] Data register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
always having the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B or C.
Read /Write
Reset Value: 0000 0000 (00h)
7
0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
Bit 7:0 = DD[7:0] Data direction register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B or C.
Read /Write
Reset Value: 0000 0000 (00h)
7
0
O7 O6 O5 O4 O3 O2 O1 O0
Bit 7:0 = O[7:0] Option register 8 bits.
For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.
The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
Input mode:
0: Floating input
1: Pull-up input with or without interrupt
Output mode:
0: Output open drain (with P-Buffer deactivated)
1: Output push-pull (when available)
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