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ST7MDT1-DVP2 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST7MDT1-DVP2' PDF : 140 Pages View PDF
ST72104G, ST72215G, ST72216G, ST72254G
11 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
11.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows having two ful-
ly independent external interrupt source sensitivi-
ties with configurable sources (using EXTIT option
bit) as shown in Figure 23 and Figure 24.
Each external interrupt source can be generated
on four different events on the pin:
s Falling edge
s Rising edge
s Falling and rising edge
s Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.
11.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
s Main clock signal (fCPU) output on PC2
s SPI pin configuration:
– SS pin internal control to use the PB7 I/O port
function while the SPI is active.
– Master output capability on MOSI pin (PB4)
deactivated while the SPI is active.
– Slave output capability on MISO pin (PB5) de-
activated while the SPI is active.
These functions are described in detail in the Sec-
tion 11.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 37.
Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1
PA7
ei0
IS00 IS01
INTERRUPT
PA0
SOURCE
SENSITIVITY
PC5
CONTROL
PC0
MISCR1
ei1
IS10 IS11
PB7
INTERRUPT
SOURCE
SENSITIVITY
CONTROL
PB0
Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1
ei0
IS00 IS01
PA7
INTERRUPT
SOURCE
SENSITIVITY
CONTROL
PA0
MISCR1
PB7
ei1
IS10 IS11
INTERRUPT
PB0
SOURCE
SENSITIVITY
PC5
CONTROL
PC0
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