ST8004CD View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST8004CD' PDF : 19 Pages View PDF
ST8004
be tied to pin VUP, thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the
capacitor between pins S1 and S2 may be omitted.
VOLTAGE SUPERVISOR (FOR VTHSEL = VDD OR FLOATING)
This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for
maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.1). As long
as VDD is less than Vth2 +Vhys(th2), the IC will remain inactive whatever the levels on the command lines.
This also lasts for the duration of tW after VDD has reached a level higher than Vth2 +Vhys(th2).The system
controller should not attempt to start an activation sequence during this time. When VDD falls below Vth2,
a deactivation sequence of the contacts is performed.
VOLTAGE SUPERVISOR (FOR VTHSEL = GND)
This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for
maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.2). If VDD
is less than Vth3 during a time, longer than ∆THFIL (max 150µs), the IC will remain inactive whatever the
levels on the command lines. The IC remain inactive also for the duration of tw after VDD has reached a
level higher than Vth3. The system controller should not attempt to start an activation sequence during this
time. When VDD falls below Vth3 during time more than ∆THFIL, a deactivation sequence of the contacts is
performed.
CLOCK CIRCUITRY
The clock signal (CLK) to the card is either derived from a clock signal input on the pin XTAL1 or from a
crystal up to 26 MHz connected between pins XTAL1 and XTAL2.
The frequency may be chosen at fXTAL,1/2 fXTAL,1/4 fXTAL or 1/8 fXTAL via pins CLKDIV1 and CLKDIV2
(see Table 1). The frequency change is synchronous, which means that during transition, no pulse is
shorter than 45% of the smallest period and that the first and last clock pulse around the change has the
correct width.
In the case of fXTAL, the duty factors depend on the signal at XTAL1.
In order to reach a 45% to 55% duty factor on the pin CLK the input signal on XTAL1 should have a duty
factor of 48% to 52% and transition times of less than 5% of the input signal period.If a crystal is used with
fXTAL, the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal
characteristics and frequency. In the other cases, it is guaranteed between 45% and 55% of the period.
The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock
pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing
diagram of the activation sequence. If the signal applied to XTAL1 is controlled by the micro-controller,
then the clock pulse will be applied to the card by the microcontroller after completion of the activation
sequence.
TABLE 1
CLKDIV1
0
0
1
1
CLKDIV2
0
1
1
0
CLK
1/8 fXTAL
1/4 fXTAL
1/2 fXTAL
fXTAL
I/O CIRCUITRY
The three data lines I/O, AUX1 and AUX2 are identical. The Idle state is realized by data lines I/O and I/
OUC being pulled HIGH via a 10k resistor (I/O to VCC and I/OUC to VDD ). I/O is referenced to VCC, and
I/OUC to VDD, thus allowing operation with VCC ≠ VDD. The first line on which a falling edge occurs
becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which
then becomes the slave. After a time delay td (edge) (approximately 200 ns), the N transistor on the slave
line is turned on, thus transmitting the logic 0 present on the master line.When the master line returns to
logic 1, the P transistor on the slave line is turned on during the time delay td (edge) and then both lines
return to their idle state. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to
deliver more than 1 mA up to an output voltage of 0.9 VCC on a 80pF load. At the end of the active pull-up
12/19
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