ST90158 - SERIAL PERIPHERAL INTERFACE (SPI)
9.4 SERIAL PERIPHERAL INTERFACE (SPI)
9.4.1 Introduction
The Serial Peripheral Interface (SPI) is a general
purpose on-chip shift register peripheral. It allows
communication with external peripherals via an
SPI protocol bus.
In addition, special operating modes allow re-
duced software overhead when implementing I2C-
bus and IM-bus communication standards.
The SPI uses up to 3 pins: Serial Data In (SDI),
Serial Data Out (SDO) and Synchronous Serial
Clock (SCK). Additional I/O pins may act as device
selects or IM-bus address identifier signals.
The main features are:
s Full duplex synchronous transfer if 3 I/O pins are
used
Figure 64. Block Diagram
SDO
s Master operation only
s 4 Programmable bit rates
s Programmable clock polarity and phase
s Busy Flag
s End of transmission interrupt
s Additional hardware to facilitate more complex
protocols
9.4.2 Device-Specific Options
Depending on the ST9 variant and package type,
the SPI interface signals may not be connected to
separate external pins. Refer to the Peripheral
Configuration Chapter for the device pin-out.
SDI SCK/INT2
READ BUFFER
SERIAL PERIPHERAL INTERFACE DATA REGISTER
*
( SPIDR )
R253
END OF
TRANSMISSION
MULTIPLEXER
POLARITY
PHASE
BAUD RATE
INTCLK
SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0
R254
ST9 INTERRUPT
INTB0
SERIAL PERIPHERAL CONTROL REGISTER ( SPICR )
* Common for Transmit and Receive
n
DATA BUS
INT2
1
0
INTERNAL
SERIAL
CLOCK
TO MSPI
CONTROL
LOGIC
VR000347
131/190
9