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ST90135M5Q6 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST90135M5Q6' PDF : 190 Pages View PDF
ST90158 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Bit 2 = CPHA: Transmission Clock Phase.
CPHA controls the relationship between the data
on the SDI and SDO pins, and the clock signal on
the SCK pin. The CPHA bit selects the clock edge
used to capture data. It has its greatest impact on
the first bit transmitted (MSB), because it does (or
does not) allow a clock transition before the first
data capture edge. Figure 74 shows the relation-
ship between CPHA, CPOL and SCK, and indi-
cates active clock edges and strobe times.
CPOL
0
0
1
1
CPHA
0
1
0
1
SCK
(in Figure 74)
(a)
(b)
(c)
(d)
Bit 1:0 = SPR[1:0]: SPI Rate.
These two bits select one (of four) baud rates, to
be used as SCK.
SPR1
SPR0
Clock
Divider
0
0
8
0
1
16
1
0
128
1
1
256
SCK Frequency
(@ INTCLK = 12MHz)
1500kHz
750kHz
93.75kHz
46.87kHz
(T = 0.67µs)
(T = 1.33µs)
(T = 10.66µs)
(T = 21.33µs)
Figure 74. SPI Data and Clock Timing
140/190
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