ST90135M5Q6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST90135M5Q6' PDF : 190 Pages View PDF
ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK CONTROL REGISTERS (Cont’d)
PLL CONFIGURATION REGISTER (PLLCONF)
R246 - Read/Write
Register Page: 55
Reset Value: xx00 x111
7
0
-
- MX1 MX0 - DX2 DX1 DX0
Bit 5:4 = MX[1:0]: PLL Multiplication Factor.
Refer to Table 13 for multiplier settings.
WARNING: After these bits are modified, take
care that the PLL lock-in time has elapsed before
setting the CSU_CKSEL bit in the CLK_FLAG reg-
ister.
Bit 2:0 = DX[2:0]: PLL output clock divider factor.
Refer to Table 14 for divider settings.
Table 13. PLL Multiplication Factors
MX1
1
0
1
0
MX0
0
0
1
1
CLOCK2 x
14
10
8
6
Table 14. Divider Configuration
DX2 DX1 DX0
CK
0
0
0
PLL CLOCK/1
0
0
1
PLL CLOCK/2
0
1
0
PLL CLOCK/3
0
1
1
PLL CLOCK/4
1
0
0
PLL CLOCK/5
1
0
1
PLL CLOCK/6
1
1
0
PLL CLOCK/7
1
1
1
CLOCK2
(PLL OFF, Reset State)
Figure 36. RCCU General Timing
User program execution
External
Reset
Filtered
External
Reset
CLOCK2
Boot ROM execution
20µs
< 4µs Reset phase
PLL Multiplier
clock
Internal
Reset
PLL switched on by user
PLL selected by user
INTCLK
510 x CLOCK1
PLL Lock-in
time
Exit from RESET
VR02113B
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