ST95022 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST95022' PDF : 16 Pages View PDF
Figure 5. Block Diagram
HOLD
W
S
C
D
Q
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
Status
ST95022
Block
Protect
16 Bytes
X Decoder
AI01272
tected blocks. The blocks and respective WRSR
control bits are shown in Table 4.
When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.
This rising edge of S must appear no later than the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.
Table 4. Write Protected Block Size
Status Register
Bits
BP1
BP0
Array
Addresses
Protected
Protected
Block
0
0
none
none
0
1
C0h - FFh
Upper quarter
1
0
80h - FFh
Upper half
1
1
00h - FFh Whole memory
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