
Figure 7. Write Enable Latch Sequence
S
01234567
C
D
HIGH IMPEDANCE
Q
AI01441
ST95022
Figure 8. Byte Write Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
C
INSTRUCTION
BYTE ADDRESS
DATA BYTE
D
A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
Q
AI01559
7/16