STA003T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA003T' PDF : 32 Pages View PDF
STA003T
DRA
Address: 0x48
Type: R/W
Software Reset: 0X00
Hardware Reset: 0X00
MSB
b7
DRA7
0
0
0
:
0
b6
DRA6
0
0
0
:
1
b5
DRA5
0
0
0
:
1
b4
DRA4
0
0
0
:
0
b3
DRA3
0
0
0
:
0
b2
DRA2
0
0
0
:
0
b1
DRA1
0
0
1
:
0
LSB
b0
DRA0
0
1
0
:
0
Description
OUTPUT ATTENUATION
NO ATTENUATION
-1dB
-2dB
:
-96dB
DRA register is used to attenuate the level of
audio output at the Right Channel using the but-
terfly shown in Fig. 11. When the register is set to
255 (0xFF), the maximum attenuation is
achieved.
A decimal unit correspond to an attenuation step
of 1 dB.
DRB
Address: 0x49
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
MSB
b7
DRB7
0
0
0
:
0
b6
DRB6
0
0
0
:
1
b5
DRB5
0
0
0
:
1
b4
DRB4
0
0
0
:
0
b3
DRB3
0
0
0
:
0
b2
DRB2
0
0
0
:
0
b1
DRB1
0
0
1
:
0
LSB
b0
DRB0
0
1
0
:
0
Description
OUTPUT ATTENUATION
NO ATTENUATION
-1dB
-2dB
:
-96dB
DRB register is used to re-direct the Right Chan- Default value is 0x00, corresponding at the maxi-
nel on the Left, or to mix both the Channels.
mum attenuation in the re-direction channel.
PCMDIVIDER
Address: 0x54
Type: RW
Software Reset: 0x01
Hardware Reset: 0x01
7
6
5
4
3
2
1
0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
DACs), and the SCKT (Serial Audio Transmitter
Clock).
The relation is the following:
SCKT_freq
=
2
(1
OCLK_freq
+ PCMDIVIDER)
PCMDIVIDER is used to set the frequency ratio
between the OCLK (Oversampling Clock for
18/32
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