STA003T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA003T' PDF : 32 Pages View PDF
STA003T
5.4. TIMING DIAGRAMS
5.4.1. Audio DAC Interface
a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO
tsdo
SCKT
tsckt
LRCLK
tlrclk
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing
(Cload_ OCLK)
tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing
(Cload_ OCLK)
tlrckt = 3.5 + pad_timing (Cload_LRCCKT) -
pad_timing (Cload_ OCLK)
D98AU969
Pad-timing versus load
Load (pF)
Pad_timing
25
2.90ns
50
3.82ns
75
4.68ns
100
5.52ns
Cload_XXX is the load in pF on the XXX output.
pad_timing (Cload_XXX) is the propagation delay
added to the XXX pad due to the load.
b) OCLK in input.
OCLK (INPUT)
thi
tlo
SDO
SCKT
LRCLK
tsdo
tsckt
tlrclk
toclk
Thi min = 3ns
Tlo min = 3ns
Toclk min = 25ns
tsdo = 5.5 + pad_timing (Cload_SDO) ns
tsckt = 6 + pad_timing (Cload_SCKT) ns
tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns
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