STA015 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA015' PDF : 44 Pages View PDF
STA015-STA015B-STA015T
ANCILLARY DATA BUFFER
Address: 0x7E - 0xB5 (126 - 181)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
The STA015 contains 56 consecutive 8-bit regis-
ters corresponding to the maximum number of
ancillary data that may be contained in MPEG
frame.
The ANCCOUNT_L and ANCOUNT_H registers
contain the number of ancillary data bits available
within the current MPEG frame.
To perform ancillary data reading a status regis-
ter (0xB6 - INTERRUPT_STATUS_REGISTER)
is available: bit 0 of this register should be polled
by the microcontroller in order to understand
when new data are available.
0x7E
----
----
----
----
0xB5
ANC_DATA_1
---------
---------
---------
---------
ANC_DATA_56
0xB6
ISR
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2
b1
b0
X X X X AA1 AA0 ASM_EN AFM_EN
This register controls ADPCM engine and how
data must be compressed.
AFM_EN ADPCM Frame Mode Enable
0 = no frames (raw format)
1 = select the framed output format for
ADPCM encoded data
ASM_EN: ADPCM Stereo Mode Enable
0 = Disable stereo mode
1 = Enable stereo mode
AA0,AA1:
ADPCM Algorithm selection
The ADPCM encoding/decoding algorithm
can be selected according to the following
table:
AA1
0
0
1
1
AA0
0
1
0
1
DVI algorithm
G723-24 algorithm (24kbp/s)
G721 algorithm (32kbp/s)
G723-40 algorithm (40kbp/s)
ISR
Address: 0xB6 (182)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
XXXXXXX 0
1
X = don’t care;
0 = no ancillary data
1 = Ancillary Data Available
The ISR is used by the microcontroller to under-
stand when a new ancillary data block is avail-
able. After all ancillary data has been retrieved
this bit must be cleared.
ADPCM_CONFIG
Address: 0xB8 (184)
Type: R/W
The above bitrates refers to an 8 KHz 16 bits
mono input stream.
Please note that 32KHz stereo mode is only
available (both in encoding and decoding) with
DVI algorithm
GPSO_ENABLE
Address: 0xB9 (185)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7 b6 b5 b4 b3 b2 b1 b0
X X X X X X X GEN
This register enable/disable the GPSO interface.
Setting the GEN bit will enable the serial interface
for ADPCM data retrieving. Reset GEN bit to dis-
able GPSO interface.
31/44
Share Link: 
