STA309B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA309B' PDF : 66 Pages View PDF
STA309B
5
I2C bus operation
I2C bus operation
The STA309B supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA309B is always a slave device in all of its communications.
5.1
5.1.1
5.1.2
5.1.3
5.1.4
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition
while the clock is high is used to identify a START or STOP condition.
Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between the
STA309B and the bus master.
Data input
During the data input the STA309B samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
5.2
Device addressing
To start communication between the master and the Omega FFX core, the master must
initiate with a start condition. Following this, the master sends 8 bits to the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA309B the I2C interface has two device addresses depending on the SA
port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
for write mode. After a START condition, the STA309B identifies on the bus the device
address and if a match is found, it acknowledges the identification on the SDA bus during
Doc ID 022570 Rev 2
15/66
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