STA309B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA309B' PDF : 66 Pages View PDF
I2C bus operation
STA309B
the 9th-bit time. The byte following the device identification byte is the internal space
address.
5.3
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA309B acknowledges this and then waits for the byte of internal address.
After receiving the internal byte address the STA309B again responds with an
acknowledgement.
5.3.1
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the FFX
core. The master then terminates the transfer by generating a STOP condition.
5.3.2
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4. Write mode sequence
BYTE
WRITE
START
MULTIBYTE
WRITE
START
DEV-ADDR
DEV-ADDR
ACK
RW
ACK
RW
ACK
SUB-ADDR
ACK
SUB-ADDR
DATA IN
DATA IN
ACK
STOP
ACK
DATA IN
ACK
STOP
Figure 5. Read mode sequence
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
START
START
START
START
DEV-ADDR
DEV-ADDR
DEV-ADDR
ACK
RW
ACK
RW
RW= ACK
HIGH
DEV-ADDR
ACK
RW
DATA
SUB-ADDR
DATA
NO ACK
STOP
ACK
DEV-ADDR
S TAR T
ACK
DATA
SUB-ADDR
ACK
S TAR T
DEV-ADDR
ACK
RW
ACK
ACK
RW
DATA
DATA
DATA
NO ACK
STOP
NO ACK
STOP
ACK
DATA
ACK
NO ACK
DATA
STOP
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Doc ID 022570 Rev 2
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