STA310 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STA310

6+2-CH. MULTISTANDARD AUDIO DECODER

STMicroelectronics 

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4.2 Clocks

There are two embedded PLLs in the STA310: the system PLL and the PCM PLL.

The following is the block diagram of the system and audio clocks used in the STA310

Figure 3. PLL Block Diagram

CLKOUT

CLK

RXN RXP

PCMCLK

STA310

/N

sys_clockout PLL Sys

PLL Audio

SPDIF

78

plls_config

sys_clk

DSP Core

pcm_clk

PCM_OUT

SCLOCK

LRCLK

PCMOUT0,1,2,3

Periph 1

R

Periph 2

Periph 3

I

W

Figure 4. Block Diagram of Functional PLL

ClkIn

(27MHz)

DIV N+1

PFD

pll_disable

DIV M+1

dN

Frac

Switching

Circuit

update_frac

analog part

Charge Ip

Pump

VCO

Uvco

DIV (X+1)

Oclk

Filter (external)

R

C3 C

11/90

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