STA310 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STA310' PDF : 90 Pages View PDF
STA310
Table 4.
Bit 0
Bit 1
Bit 2
Bit 3
When Set
The input data is one slot delayed with
respect to LRCLKIN
First channel when LRCLKIN is set
Data are sampled on falling edge of
DSTR
All the bytes are extracted
When Clear
The input data is not delayed
First channel when LRCLKIN is reset
Data are sampled on rising edge of
DSTR
Only the first 16 data bits are extracted
Name
DelayMode
LeftFirstChannel
FallingStrobe
AllSlot
Figure 7.
LRCLKIN
DSTR
SIN
00000000000
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0000000000000
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00
00
00
00
0
0
0
0
0
0
00000000000
Transferred data
Discarded data
Example 2: Only the first 2 bytes are transferred to the STA310 because the number of slots is 20 (16 + 4). SIN
and LRCLKIN are sampled on the falling edge of DSTR. The data is in delayed mode.
The register configuration is SIN_SETUP=3 and CAN_SETUP = DelayMode + LeftFirstChannel + FallingStrobe
+ AllSlot = 1 + 2 + 4 + 8 = 15.
This mode is a specific mode where only the first 16 data bits are transferred. The remaining bits are discarded.
The register configuration is SIN_SETUP = 3 and CAN_SETUP = DelayMode + FallingStrobe = 1 + 4 = 5.
4.4.1.3 SPDIF Input
A true SPDIF Input SPDIF (PCM audio samples) or IEC-61937 (compressed data) is selectable as a main serial
input.
4.4.1.4 Autodetected formats
The STA310 cut 2.0 is able the following audio format changes on the s/pdif input
Table 5. Audio Format detection
BEFORE
AC3
AC3
MPEG
MPEG
PCM
PCM
AFTER
PCM
MPEG
AC3
PCM
AC3
MPEG
16/90
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