STA333BW View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STA333BW
STMicroelectronics
'STA333BW' PDF : 67 Pages View PDF
STA333BW
Register description
6.1.5
Configuration register E (addr 0x04)
D7
SVE
1
D6
ZCE
1
D5
DCCV
0
D4
PWMS
0
D3
AME
0
D2
NSBW
0
D1
MPC
1
Max power correction variable
Table 34. Max power correction variable
Bit R/W RST
Name
Description
0
R/W
0
MPCV
0: use standard MPC coefficient
1: use MPCC bits for MPC coefficient
D0
MPCV
0
Max power correction
Table 35. Max power correction
Bit R/W RST
Name
1
R/W
1
MPC
Description
0: function disabled
1: enables power bridge correction for THD
reduction near maximum power output.
Setting the MPC bit turns on special processing that corrects the STA333BW power device
at high power. This mode should lower the THD+N of a full FFX system at maximum power
output and slightly below. If enabled, MPC is operational in all output modes except tapered
(OM[1,0] = 01) and binary. When OCFG = 00, MPC has no effect on channels 3 and 4, the
line-out channels.
Noise-shaper bandwidth selection
Table 36. Noise-shaper bandwidth selection
Bit R/W RST
Name
2 R/W 0
NSBW
1: third-order NS
0: fourth-order NS
Description
AM mode enable
Table 37. AM mode enable
Bit R/W RST
Name
3 R/W 0
AME
Description
0: normal FFX operation.
1: AM reduction mode FFX operation
STA333BW features a FFX processing mode that minimizes the amount of noise generated
in frequency range of AM radio. This mode is intended for use when FFX is operating in a
device with an AM tuner active. The SNR of the FFX processing is reduced to approximately
83 dB in this mode, which is still greater than the SNR of AM radio.
Doc ID 13773 Rev 3
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