STA333BW View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STA333BW
STMicroelectronics
'STA333BW' PDF : 67 Pages View PDF
Register description
STA333BW
The PWDN register is used to place the IC in a low-power state. When PWDN is written
as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted
to power down the power-stage, then the master clock to all internal hardware expect the
I2C block is gated. This places the IC in a very low power consumption state.
External amplifier power down
Table 49. External amplifier power down
Bit R/W RST
Name
Description
7
R/W
0
EAPD
0: external power stage power down active
1: normal operation
The EAPD register directly disables / enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled). This
register also controls the FFX4B / EAPD output pin when OCFG = 10.
6.2
Volume control registers (addr 0x06 - 0x0A)
The volume structure of the STA333BW consists of individual volume registers for each
channel and a master volume register that provides an offset to each channels volume
setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB
to -80 dB.
As an example if C3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain
for channel 3 = +36 dB.
The channel mutes provide a “soft mute” with the volume ramping down to mute in
4096 samples from the maximum volume setting at the internal processing rate
(approximately 96 kHz).
A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) in any
channel volume register. When volume offsets are provided via the master volume register
any channel whose total volume is less than -80 dB is muted.
All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E
(addr 0x04)) on a per channel basis as this creates the smoothest possible volume
transitions. When ZCE = 0, volume updates occur immediately.
40/67
Doc ID 13773 Rev 3
Share Link: 