STA3398 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STA3398

2.1-channel high-efficiency digital audio system / PowerSSO-36 slug down Package

STMicroelectronics 

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Electrical specifications

3.6

Power on/off sequence

Figure 3. Power-on sequence

Note: no specific VCC and

VDD_DIG turnon sequence

is required

VCC

VDD_Dig

Don’t care

STA339BW

Note:

XTI

Reset

Don’t care

TR

TC

I2C

Don’t care

CMD0 CMD1 CMD2

PWDN

TR = minimum time between XTI master clock stable and Reset removal: 1 ms

TC = minimum time between Reset removal and I2C program, sequence start: 1ms

The definition of a stable clock is when fmax - fmin < 1 MHz.

Section 7.2.3 on page 31 gives information on setting up the I2S interface.

Figure 4. Power-off sequence for pop-free turn-off

Note: no specific VCC and

VDD_DIG turnoff sequence

is required

VCC

VDD_Dig

Don’t care

XTI

Soft Mute

Reg. 0x07

Data 0xFE

Soft EAPD

Reg. 0x05

Bit 7 = 0

Don’t care

FE

Don’t care

Don’t care

18/78

DocID15251 Rev 7

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