STA3398 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STA3398
STMicroelectronics
'STA3398' PDF : 78 Pages View PDF
Serial audio interface
4
Serial audio interface
STA339BW
4.0.1
The STA339BW audio serial input interface was designed to interface with standard digital
audio components and to accept a number of serial data formats. The STA339BW always
acts as the slave when receiving audio input from standard digital audio components. Serial
data for two channels is provided using three inputs: left/right clock LRCKI, serial clock
BICKI, and serial data SDI12.
The SAI bit and the SAIFB bit are used to specify the serial data format. The default serial
data format is I2S, MSB-first.
Timings
In the STA339BW the BICKI and LRCKI pins are configured as inputs and they must be
supplied by the external peripheral.
Figure 7. Timing diagram for SAI interface
BICKI
LRCKI
SDI12
tBCH
tBCL
tBCy
80%
40%
tLRH
tLRSU
4.0.2
4.0.3
Table 9. Timing parameters for slave mode
Symbol
Parameter
Min
tBCy BICK cycle time
80
tBCH BICK pulse width high
40
tBCL BICK pulse width low
40
tLRSU LRCKI setup time to BICKI strobing edge
40
tLRH LRCKI hold time to BICKI strobing edge
40
tLRJT LRCKI Jitter Tolerance
Typ Max Unit
-
- ns
-
- ns
-
- ns
-
- ns
-
- ns
40 ns
Delay serial clock enable
To tolerate anomalies in some I2S master devices, a PLL clock cycle delay can be added to
the BICKI signal before the SAI interface.
Channel input mapping
Each channel received via I2S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I2S input channel to its corresponding processing channel.
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DocID15251 Rev 7
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