STA3398 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STA3398

2.1-channel high-efficiency digital audio system / PowerSSO-36 slug down Package

STMicroelectronics 

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STA339BW

Register description

7.6.2

7.6.3

Invalid input detect mute enable

Bit R/W

2

R/W

Table 47. Invalid input detect mute enable

RST

Name

Description

1

IDE

Setting of 1 enables the automatic invalid input

detect mute

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

Binary output mode clock loss detection

Bit R/W

3

R/W

Table 48. Binary output mode clock loss detection

RST

Name

Description

1

BCLE

Binary output mode clock loss detection enable

7.6.4

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

LRCK double trigger protection

Bit R/W

4

R/W

Table 49. LRCK double trigger protection

RST

Name

Description

1

LDTE

LRCLK double trigger protection enable

7.6.5

Actively prevents double trigger of LRCLK.

Auto EAPD on clock loss

Bit R/W

5

R/W

Table 50. Auto EAPD on clock loss

RST

Name

Description

0

ECLE

Auto EAPD on clock loss

7.6.6

When active, issues a power device power down signal (EAPD) on clock loss detection.

IC power down

Bit R/W

7

R/W

Table 51. IC power down

RST

Name

Description

1

PWDN

0: IC power down low-power condition

1: IC normal operation

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

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