STA3398 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STA3398

2.1-channel high-efficiency digital audio system / PowerSSO-36 slug down Package

STMicroelectronics 

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Register description

Table 55. Channel volume as a function of CxV[7:0]

CxV[7:0]

Volume

00000000 (0x00)

00000001 (0x01)

00000010 (0x02)

…

01011111 (0x5F)

01100000 (0x60)

01100001 (0x61)

…

11010111 (0xD7)

11011000 (0xD8)

11011001 (0xD9)

11011010 (0xDA)

…

11101100 (0xEC)

11101101 (0xED)

…

11111111 (0xFF)

+48 dB

+47.5 dB

+47 dB

…

+0.5 dB

0 dB

-0.5 dB

…

-59.5 dB

-60 dB

-61 dB

-62 dB

…

-80 dB

Hard channel mute

…

Hard channel mute

STA339BW

7.8

7.8.1

48/78

Audio preset registers (addr 0x0B and 0x0C)

Audio preset register 1 (addr 0x0B)

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

AMGC[1]

AMGC[0]

Reserved

0

0

0

0

0

0

0

0

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 66.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00 then bits AMGC[1:0] are defined below in Table 56.

Table 56. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0]

Mode

00

User programmable GC

01

AC no clipping 2.1

10

AC limited clipping (10%) 2.1

11

DRC night-time listening mode 2.1

DocID15251 Rev 7

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