STCN75DS2F View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STCN75DS2F' PDF : 35 Pages View PDF
STCN75
Figure 15. Bus timing requirements sequence
DC and AC parameters
SDA
tBUF
SCL
P
tHD:STA
tR
tF
tHIGH
S
tLOW
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
SR
tSU:STO
P
AI00589
Table 13. AC characteristics
Sym
Parameter(1)(2)
Min Max Unit
fSCL SCL clock frequency
tBUF Time the bus must be free before a new transmission can start
tF
SDA and SCL fall time
tHD:DAT(3) Data hold time
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
0 400 kHz
1.3
µs
300 ns
0
µs
600
ns
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
Clock high period
Clock low period
SDA and SCL rise time
Data setup time
START condition setup time
(only relevant for a repeated start condition)
600
ns
1.3
µs
300 ns
100
ns
600
ns
tSU:STO STOP condition setup time
600
ns
1. Valid for ambient operating temperature: TA = –55 to 125 °C; VDD = 2.7 V to 5.5 V (except where noted).
2. Devices are tested at maximum clock frequency of 400 kHz.
3. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL
Doc ID 13307 Rev 9
29/36
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