STE10 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STE10' PDF : 66 Pages View PDF
Table 21. PCI Timing
Symbol
Parameter
Tsu Input Set up Time to Clock
(bussed signals)
Tsu(ptp) Input Set up Time to Clock
(point to point)
Th Input Hold Time from Clock
Th Input Hold Time from Clock
Trst Reset Active Time after Power
Stable
Trst-clk Reset Active Time after CLK
Stable
Trst-off Reset Active to Output Float
delay
Figure 17. PCI Timings
Test Condition
STE10/100
Min.
7
Typ.
Max.
Units
ns
10,12
ns
0
ns
0
ns
1
ms
100
µs
40
ns
1.5V
CLK
OUTPUT Delay
Tval
1.5V
Tri-state OUTPUT
Ton
Tsu
Toff
Th
INPUT 1.5V
1.5V
2.4V
0.4V
61/66
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