Figure 19. Flash read timings
ADDRESS
CS#
OE#
DATA
Tfcyc
Tfce
Tfoe
Tfasd
STE10/100
Tfdf
Table 23. EEPROM Interface Timings
Symbol
Parameter
Tscf Serial Clock Frequency
Tecss Delay from CS High to SK High
Tecsh Delay from SK Low to CS Low
Tedts Setup Time of DI to SK
Tedth Hold Time of DI after SK
Tecsl CS Low Time
Figure 20. Serial EEPROM timing
Test Condition
Min. Typ. Max. Units
CS
CLK
Tecss
Tedts
Tecsh
Tecsl
Tedth
DI
63/66