STE100A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STE100A' PDF : 82 Pages View PDF
STE10/100A
Registers and descriptors description
Table 6. Configuration registers description (continued)
Bit #
Name
Description
Capability identifier. This value is always 01h,
7~0
CAPID indicating the link list item as being the PCI power
management registers.
CR49 (offset = c4h), PMR1, Power management register 1
31~16
--- Reserved
15
14,13
PMEST
PME_Status. This bit is set whenever the
STE10/100A detects a wake-up event, regardless of
the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the
STE10/100A to deassert PME# (if so enabled).
Writing a “0” has no effect.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not
support PME# generation from D3cold), this bit is by
default 0; otherwise, PMEST is cleared upon power-
up reset only and is not modified by either hardware
or software reset.
DSCAL
Data_Scale. Indicates the scaling factor to be used
when interpreting the value of the data register. This
field is required for any function that implements the
data register.
The STE10/100A does not support data register and
Data_Scale.
12~9
DSEL
Data_Select. This four bit field is used to select
which data is to be reported through the data
register and Data_Scale field. This field is required
for any function that implements the data register.
The STE10/100A does not support Data_select.
PME_En. When set, enables the STE10/100A to
assert PME#. When cleared, disables the PME#
assertion.
8
PME_En If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not
support PME# generation from D3cold), this bit is by
default 0; otherwise, PME_En is cleared upon power
up reset only and is not modified by either hardware
or software reset.
Default
01h
X
00b
0000b
X
RW type
RO
R/W1C(1)
RO
R/W
R/W
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