STE100A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STE100A' PDF : 82 Pages View PDF
STE10/100A
Figure 17. PCI timings
CLK
0.4Vcc
OUTPUT delay
Electrical specifications and timings
Tval
.
0.4Vcc
0.6Vcc
0.2Vcc
Tri-state OUTPUT
Ton
Tsu
INPUT 0.4Vcc
0.4Vcc
Toff
Th
0.6Vcc
0.4Vcc
0.2Vcc
Table 23. Flash interface timings
Symbol
Parameter
Tfcyc Read/write cycle time
Tfce
Address to read data setup
time
Tfce CS# to read data setup time
Tfoe
OE# active to read data
setup time
Tfdf
OE# inactive to data driven
delay time
Tfas
Address setup time before
WE#
Tfah Address hold time after WE#
Tfcs CS# setup time before WE#
Tfch Address hold time after WE#
Tfds Data setup time
Tfdh Data hold time
Tfwpw Write pulse width
Tfwph Write pulse width high
Tfasc
Address setup time before
CS#
Tfahc Address hold time after CS#
Test condition
Min.
Typ. Max. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75/82
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