Electrical specifications and timings
Figure 18. Flash write timings
Tfcyc
ADDRESS
Tfasc
Tfasw
Tfah
Tahw
CS#
WE#
DATA
Tfcss
Tfwph
Tfwpw
Tfcsh
Tfds
Tfdh
STE10/100A
Figure 19. Flash read timings
ADDRESS
Tfcyc
CS#
OE#
DATA
Tfce
Tfoe
Tfdf
Tfasd
Table 24. EEPROM Interface Timings
Symbol
Parameter
Test condition
Tscf
Tecss
Tecsh
Serial clock frequency
Tscf - 1.4 µs
Delay from CS high to SK
high
Delay from SK low to CS low
Tedts Setup time of DI to SK
Tedth Hold time of DI after SK
Tecsl CS low time
Min.
0.1
200
200
0
0.5
Typ. Max. Units
714
kHz
1.7
µs
650
ns
600
ns
700
ns
1.1
µs
76/82