STLC1502 View Datasheet(PDF) - STMicroelectronics
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Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
6.5.1 The DMA Descriptors Chain
The Descriptor list is the mean the CPU and the DMA_MAC use to communicate each other in order to
transmit/receive frames on the cable. This list must be properly prepared before initiating any transfer
activity to/from the cable. The Descriptor is produced by the CPU and consumed by the DMA_MAC.
DMA_Cntl
DMA_Addr
DMA_Next
Tx/Rx_Status
Descr 1
(4 X 4 Bytes)
DMA_Cntl
DMA_Addr
DMA_Next
Tx/Rx_Status
Descr 2
(4 X 4 Bytes)
...
DMA_Cntl
DMA_Addr
DMA_Next
Tx/Rx_Status
Descr n
(4 X 4 Bytes)
Frame 0
Frame 1
Frame n
• A Descriptor is a 16-bytes element which provides the DMA_MAC with information about how to
transmit/receive a single frame and how to report the transfer status back to the CPU.
• A Descriptor can be stored in any main memory location with a 32-bit aligned address.
• The first 3 words stored in a Descriptor are expected to be the values of the 3 DMA_MAC registers
describing a DMA transfer (DMA_Cntl, DMA_Addr and DMA_Next). When the DMA_MAC fetches a
Descriptor it loads this three values into its own corresponding registers.
• The last word is to be used by the DMA_MAC to report the transfer status.
6.5.2 The Descriptor control bits
The Descriptor keeps information about a single frame transfer and how to access the next Descriptor.
The following discussion is related to 3 bits of the Descriptor: the VALID bit, the NXT_EN bit and the
NPOL_EN bit.
The Descriptor can be accessed simultaneously by the CPU and the DMA_MAC. This concurrent access
is synchronized by the VALID bit in the DMA_Cntl register. When the VALID bit is equal to 0 then the
CPU is the owner of the Descriptor. Otherwise the owner is the DMA_MAC. Since the Descriptor can be
accessed in write mode by the owner only at any time, race conditions are guaranteed to never happen.
The NXT_EN bit enables the fetch of the Next Descriptor. When the DMA_MAC finds this bit set to 0 then
its activity is considered to be completed as soon as the current descriptor DMA transfers have been
completed.
The NPOL_EN bit enables the DMA_MAC to keep polling for a non-valid Descriptor until its VALID bit is
set to one. When the DMA_MAC finds both the NPOL_EN bit and the VALID bit set to 0 then its activity is
considered to be completed.
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